Cover Image for EB1 for Engineers (Critical Tech Edition)
Cover Image for EB1 for Engineers (Critical Tech Edition)
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EB1 for Engineers (Critical Tech Edition)

Hosted by Aditi Paul
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About Event

What do you do when your lawyer says you don’t qualify for EB1, even though you:

  • Work in a critical industry identified by the White House (semiconductors)

  • Hold a PhD

  • Have numerous patents and publications

That’s exactly the challenge Anantharaj Vanaraj faced. But instead of giving up, he took matters into his own hands.

Join us this Saturday to hear his inspiring journey as he shares:

  • How he overcame the “lawyer hurdle” and took control of his case

  • The strategies he used to leverage his unique profile

  • How he demonstrated his exceptional value and secured EB1 approval

  • His path to escaping the EB2 backlog and gaining freedom

This is one of the final two events on EB1 I’m conducting in 2024. Don’t miss this opportunity to learn directly from someone who turned rejection into success.

About Dr. Anatharaj:

Dr. Anantharaj Thalaimalai Vanaraj did his B.E., Electronics and Communication Engineering from Thanthai Periyar Govt. Institute of Technology, Madras University, Vellore, Tamil Nadu and M. Tech in VLSI System from National Institute of Technology, Tiruchirappalli, Tamil Nadu.

He received his Ph.D. Degree from National Institute of Technology, Tiruchirappalli in 2022. He has more than 20 years of experience in ASIC/FPGA/SOC development for consumer electronics, wireless and storage applications.

He is currently working as Formal Verification Lead with Samsung Austin Research Centre – Advanced Computing Lab (SARC-ACL), San Jose, California, USA.

He is part of the hardware design and development group for Graphics Processing Unit (GPU) at silicon level. He has delivered sessions in several international/national conferences, seminars and workshops.

He is also a senior grade member associated with Santa Clara chapter of IEEE association.

He has extensive research and development experience in NAND Flash Memory design verification using IEEE 1800 based System Verilog and UVM.

He had received six US patents related to NAND Flash Memory and SSD products. He has published more than 15+ research articles which are cited by more than 100 research articles. He is also a reviewer in various reputed international journals.

His research area involves NAND Flash Memory, Memory Architecture, CMOS VLSI Digital Design, VLSI Logic/Functional Verification, and Quantum-dot Cellular Automata (QCA) designs.

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