Latency Insensitive Design: Theoretical and Practical Considerations

​This webinar will explore Latency Insensitive Design (LID), a design paradigm developed to address the challenges of modern FPGA and ASIC systems. As die sizes increase and system complexity grows, latency becomes a major bottleneck, particularly with long distance interconnect delays and high coupling between components. LID provides effective solutions to tackle these issues.

​What you'll learn:

• ​History and Theory of LID: Understand the evolution and theoretical foundations of this design methodology.

• ​AXI4-Stream Protocol: Dive deep into the rules and waveforms of AXI4-Stream and its role in latency management.

• ​LID Infrastructure: Learn about essential components such as skid buffers, FIFOs, parallelism converters, gearboxes, and NoCs.

• ​System Design with Datapaths: Gain insights into system architecture examples using LID principles.

• ​Code Examples in SystemVerilog: See LID in action with practical code examples for FPGA and ASIC systems.